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1 for more information www.linear.com/LTC7124 typical application features description 17v, dual 3.5a synchronous step-down regulator with ultralow quiescent current the lt c ? 7124 is a dual channel, 3.5 a per output, high efficiency monolithic step- down regulator capable of operating from input supplies up to 17 v. the program- mable switching frequency ranges from 500 khz to 4mhz with a 25% external clock synchronization capability around the programmed frequency. the regulator features ultralow quiescent current for high efficiency over a wide v out range. the step-down regulator operates from an input voltage range of 3.1 v to 17 v and provides an adjustable output range from 0.6 v to 99% of v in while delivering up to 3.5a of output current per channel. a user selectable mode input is provided to allow the user to trade off output ripple for light load efficiency; burst mode ? operation provides the highest efficiency at light loads, while forced continuous operation provides the lowest output ripple. the LTC7124 includes spread spectrum modulation for low radiated and conductive noise. the LTC7124 is offered in a thermally enhanced, low profile 24-lead 3 mm 5 mm qfn package efficiency & power loss vs load current at 1mhz 1.8v/3.3v 1mhz step-down regulator applications n wide v in range: 3.1v to 17v n wide v out range: 0.6v to 99% v in n dual step-down outputs: 3.5a per channel n integrated 80m/40m n-channel mosfets provide up to 95% effciency n no-load i q < 8a with both channels enabled; i q < 5.5a with only one channel enabled n programmable frequency (500khz to 4mhz) with 25% frequency synchronization range n confgurable for a 2-phase single output at up to 7a n 1.0% output voltage accuracy n current mode operation for excellent line and load transient response n internal or programmable external loop compensation n available in a 3mm 5mm qfn-24 package n battery-powered systems n point-of-load supplies n portable instruments n handheld scanners l, lt , lt c , lt m , burst mode, linear technology, the linear logo, ltpowercad and ltspice are registered trademarks of analog devices, inc. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 6580258, 6498466, 6611131, 6177787, 5705919, 5847554. ltc 7124 7124fa c out2 100f r3 619k r4 137k l 2 1.8h c ff2 16pf c in c boost1 0.1f c out1 100f r1 619k r2 309k l 1 1.2h 47f c ff1 22pf LTC7124 7124 ta01 v in1 v in2 run1 run2 ilim gnd 2.2f fb1 fb2 sw1 sw2 boost1 boost2 intv cc ith1 ith2 rt c intvcc mode/sync v out1 1.8v at 3.5a v out2 3.3v at 3.5a v in 10.8v to 13.2v x2 v in = 12v v out = 5.0v r rt v out = 3.3v v out = 2.5v v out = 1.8v load current (a) 0 0.5 1 1.5 2 2.5 100k 3 3.5 0 10 20 30 40 50 60 70 c boost2 80 90 100 0 0.4 0.8 1.2 1.6 efficiency (%) power loss (w) 0.1f 7124 ta01a
2 for more information www.linear.com/LTC7124 pin configuration absolute maximum ratings v in 1 , v in 2 ( note 2) ..................................... C 0.3 v to 17 v run 1, run 2 .............................................. C 0.3 v to 17 v mode / sync ................................ C 0.3 v to intv cc +0.3 v i lim , rt ........................................ C0. 3 v to intv cc +0.3 v ith 1, ith 2 .................................... C 0.3 v to intv cc +0.3 v pgood 1, pgood 2 ....................................... C 0.3 v to 6v fb 1, fb 2 ....................................................... C 0.3 v to 6v operating junction temperature range ( no te 3) .............................................. C 40 c to 125 c storage temperature range .................. C 65 c to 150 c (note 1) 9 10 top view udd package variation: aa 24-lead (3mm 5mm) plastic qfn 11 12 24 25 gnd 26 gnd 23 22 21 6 5 4 3 2 1 7 15 16 17 18 19 20 14 8 13 gnd gnd v in1 i lim rt v in2 gnd gnd sw1 sw1 boost1 mode/sync intv cc boost2 sw2 sw2 fb1 ith1 pgood1 run1 fb2 ith2 pgood2 run2 t jmax = 150c, ja = 22c/w exposed pad ( pins 25 & 26) is gnd, must be soldered to pcb order information symbol parameter conditions min typ max units v in operating voltage 3.1 17 v v out output voltage (note 6) 0.6 0.99 ? v in v i q input quiescent current active mode, single channel (note 4) active mode, dual channels (note 4) burst mode, i out1 = i out2 = 0a burst mode, single channel, i out = 0a shutdown mode; v run1 = v run2 = 0v 1.5 2 8 5.5 0.1 2.75 3 16 11 1 ma ma a a a v fb regulated feedback voltage (note 5) l 0.596 0.594 0.6 0.6 0.604 0.606 v v lead free finish tape and reel part marking package description temperature range LTC7124eudd#pbf LTC7124eudd#trpbf lgvf 24-lead (3mm 5mm) plastic qfn C40c to 125c LTC7124iudd#pbf LTC7124iudd#trpbf lgvf 24-lead (3mm 5mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v in1 = v in2 = 12v, unless otherwise noted. (note 3) http://www .linear.com/product/LTC7124#orderinfo ltc 7124 7124fa
3 for more information www.linear.com/LTC7124 electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: transient absolute maximum voltages should not be applied for more than 4% of the switching duty cycle. note 3: the LTC7124 is tested under pulsed load conditions such that t j t a . the LTC7124 e is guaranteed to meet specified performance from 0 c to 85c . specifications over the C40 c to 125 c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC7124 i is guaranteed over the full C40 c to 125 c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v in1 = v in2 = 12v, unless otherwise noted. (note 3) t j is calculated from the ambient t a and power dissipation p d according to the following formula: t j = t a + (p d ? ja ) note 4: the quiescent current in active mode does not include switching loss of the power fets. note 5: the LTC7124 is tested in a proprietary test mode that connects v fb to the output of error amplifier. note 6: the maximum v out is limited by the automatic boost refresh that occurs in high duty cycle and dropout cases. the maximum v out value listed here is guaranteed by design. note 7: the minimum on-time is determined by the speed of the top switch driver and peak current comparator. the typical value listed here is guaranteed by design. symbol parameter conditions min typ max units v load&line reg output voltage load and line regulation v in = 3.1 to 17v (note 5) ith = 0.3v to 0.9v 0.3 0.5 % i fb feedback pin input current 10 na g m(ea) error amplifier transconductance ith = 0.6v 300 500 700 s t on-min minimum on time (note 7) 50 ns i sw top nmos switch leakage bottom nmos switch leakage 0.1 0.1 1 1 a a r ds(on) top nmos on resistance bottom nmos on resistance 80 40 m m v run run input high run input low 1.0 0.3 v v run input current v run = 12v 0 100 na v mode/sync pulse skip mode burst mode operation forced continuous mode intv cc C0.4 1.0 0.3 intv cc C 1.2 v v v v ilim i lim input threshold input low input high intv cc C0.3 0.2 v v i lim peak current limit i lim = 0v (both channels) i lim = intv cc (both channels) i lim = floating, channel 1 i lim = floating, channel 2 4.4 2.2 4.4 2.2 5.0 2.6 5.0 2.6 5.6 3.0 5.6 3.0 a a a a t ss internal soft start time 1100 s v intvcc v intvcc ldo output voltage v in1 > 4v 3.6 v v intvcc undervoltage lockout v in1 ramping up l 2.75 2.9 3.05 v v intvcc undervoltage lockout hysteresis 300 mv v in overvoltage lockout rising l 17.9 18.4 18.9 v v in overvoltage lockout hysteresis 500 mv f osc r t programmable oscillator frequency r rt = 100k l 0.92 1 1.08 mhz f sync sync capture range % of programmed frequency l 75 125 % power good range 5 7.5 10 % r pgood power good resistance 650 1000 t pgood pgood delay pgood low to high, r rt = 100k pgood high to low, r rt = 100k 25 32 s s ltc 7124 7124fa
4 for more information www.linear.com/LTC7124 t a = 25c, v in = 12v, l = 2.2h, f = 1mhz unless otherwise noted. typical performance characteristics efficiency vs load current for varying input supply v in1 supply current vs temperature line regulation, no load load regulation rt frequency vs temperature spread spectrum center frequency vs temperature efficiency vs load current in burst mode at 1mhz efficiency vs load current in forced continuous mode at 1mhz efficiency vs load current in forced continuous mode at 2.25mhz ltc 7124 7124fa 0.1 i q burst mode, dual temperature (c) ?50 ?25 0 25 50 75 100 125 1 0 2 4 6 8 10 12 14 16 18 10 20 v in1 supply current (ua) 7124 g05 input voltage (v) v out = 2.5v forced continuous mode 0 1 2 3 4 0 5 6 7 8 9 10 11 12 13 14 10 15 16 17 ?0.5 ?0.3 ?0.1 0.1 0.3 0.5 ?v out error (%) 20 7124 g06 v out = 3.3v forced continuous mode load current (a) 0 1 2 3 4 ?5 30 ?3 ?1 1 3 5 ?v out (%) 7124 g07 temperature (c) r rt = 100k ?50 40 ?25 0 25 50 75 100 125 0.75 0.80 0.85 50 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 frequency (mhz) 7124 g08 60 temperature (c) rt tied to intv cc ?50 ?25 0 25 50 75 100 125 v out = 1.2v* 70 1.75 1.85 1.95 2.05 2.15 2.25 2.35 2.45 2.55 2.65 80 2.75 frequency (mhz) 7124 g09 90 100 efficiency (%) 7124 g01 v out = 1.2v* v out = 2.5v v out = 3.3v v out = 5.0v v out = 2.5v load current (a) 0.001 0.01 0.1 1 10 0 10 20 30 v out = 3.3v 40 50 60 70 80 90 100 efficiency (%) 7124 g02 *l = 1h v out = 5.0v v out = 2.5v v out = 3.3v v out = 5.0v load current (a) 0.001 0.01 0.1 1 10 0 load current (a) 10 20 30 40 50 60 70 80 90 100 *l = 1h efficiency (%) 7124 g03 l = 1h v out = 1.8v l = 1.0h v in = 4v v in = 8v v in = 12v v in = 17v load current (a) 0.001 0.001 0.01 0.1 1 10 0 10 20 30 40 0.01 50 60 70 80 90 100 efficiency (%) 7124 g04 i q shutdown i q burst mode, single
5 for more information www.linear.com/LTC7124 t a = 25c, v in = 12v, l = 2.2h, f = 1mhz unless otherwise noted. typical performance characteristics reference voltage vs temperature r ds(on) vs temperature r ds(on) vs input supply voltage switch leakage current startCup with load in burst mode operation startCup into preCbiased output in burst mode operation peak current limit vs temperature load step with internal compensation load step with external compensation ltc 7124 7124fa 125 10 11 12 13 14 15 16 17 0 20 4.6 40 60 80 100 r ds, on (m) 7124 g15 top switch bottom switch temperature (c) ?50 4.7 ?25 0 25 50 75 100 125 0 2 4 4.8 6 8 10 12 14 16 sw leakage (a) 7124 g16 r v out = 5v load = 5 500s/div 5.0 run 2v/div pgood 2v/div v out 2v/div i l 1a/div 7124 g17 500s/div 5.1 run 2v/div v out 2v/div pgood 2v/div i l 1a/div 5.2 7124 g18 v out = 5v peak current limit (a) 7124 g10 v in = 12v temperature (c) v out = 2.5v i load = 100ma to 3.5a l = 1.8h ith = intv c out = 100f cc 40s/div v out ac?coupled 200mv/div i l 2a/div ?50 i load 5a/div 7124 g11 v in = 12v v out = 2.5v i load = 150ma to 3.5a l = 1.2h c ith = 150pf, r ith = 30k 10s/div v out ?25 ac?coupled 200mv/div i l 2a/div i load 5a/div 7124 g14 c out = 100f temperature (c) ?50 0 ?25 0 25 50 75 100 125 598.0 598.5 599.0 25 599.5 600.0 600.5 601.0 601.5 reference voltage (mv) 7124 g13 top switch bottom switch temperature (c) 50 ?50 ?25 0 25 50 75 100 125 0 25 75 50 75 100 125 150 r ds,on (m) 7124 g14 top switch bottom switch input voltage (v) 100 0 1 2 3 4 5 6 7 8 9
6 for more information www.linear.com/LTC7124 t a = 25c, v in = 12v, l = 2.2h, f = 1mhz unless otherwise noted. burst mode operation with full current limit burst mode operation with half current limit pulse skip mode operation i lim tied to gnd i lim tied to intv cc typical performance characteristics ltc 7124 7124fa i l 500ma/div 7124 g19 v out = 5.0v i out = 50ma 2s/div v out ac?coupled 50mv/div sw v out = 5.0v 10v/div i l 500ma/div 7124 g20 v out = 5.0v i out = 10ma 2s/div v out ac?coupled 50mv/div i out = 100ma sw 10v/div i l 500ma/div 7124 g21 2s/div v out ac?coupled 50mv/div sw 10v/div
7 for more information www.linear.com/LTC7124 pin functions gnd (pins 1, 2, 7, 8, exposed pad 25/26): the exposed pads should be soldered to pcb ground for rated thermal performance. connect all gnd pins together with solid ground plane. v in1 ( pin 3): input voltage of the channel 1 step-down regulator. this input powers the intv cc ldo. i lim (pin 4): current limit select pin. tying this pin to gnd sets full current limit for both channels. tying this pin to intv cc drops the current limit by a factor of 2 for both channels. floating this pin sets full current limit for channel 1 and half current limit for channel 2. rt (pin 5): switching frequency program pin. connect an external resistor (between 208 k to 19 k) from this pin to gnd to program the frequency from 500 khz to 4mhz, respectively. when rt is tied to intv cc , spread spectrum mode of operation will be enabled. in addition, when spread spectrum is enabled, syncing capability on the mode/ sync pin is disabled, and the part will operate in forced continuous mode around a center frequency of 2.25mhz. v in2 ( pin 6): input voltage of the channel 2 step-down regulator. may be a different voltage than v in1 . fb2 (pin 9): feedback input to the error amplifier of the channel 2 step-down regulator. connect resistor divider tap to this pin. the output voltage can be adjusted from 0.6v to 0.99 ? v in2 by: v out2 = 0.6v [1 + (r1/r2)]. ith2 (pin 10): channel 2 error amplifier output and switching regulator compensation pin. connect this pin to appropriate external components to compensate the regulator loop frequency response or to intv cc to use the default internal compensation. pgood2 (pin 11): open drain power good indicator for channel 2. run2 (pin 12): logic controlled run input to channel 2. do not leave this pin floating. logic high activates channel 2 of the step-down regulator. sw 2 ( pins 13, 14): switch node connection to the inductor of the channel 2 step- down regulator. boost2 (pin 15): boosted floating driver supply for channel 2. the (+) terminal of the bootstrap capacitor connects to this pin while the (C) terminal connects to the sw2 pin. the normal operating voltage swing of this pin ranges from intv cc to v in2 + intv cc . intv cc (pin 16): low dropout regulator. bypass with at a low esr cap of at least 2.2f to ground. mode/sync (pin 17): burst mode select and oscillator synchronization of the step-down regulator. this pin can be connected to intv cc for burst mode operation (800 ma minimum peak current clamp), gnd for pulse skipping mode (200 ma minimum peak current clamp), or between 1.0 v and intv cc C 1.2 v for forced continuous mode. furthermore, connecting mode/ sync to an external clock will synchronize the internal clock to the external clock and put the part in forced continuous mode. however, syncing capability is disabled when spread spectrum is enabled. boost1 (pin 18): boosted floating driver supply for channel 1. the (+) terminal of the bootstrap capacitor connects to this pin while the (C) terminal connects to the sw1 pin . the normal operating voltage swing of this pin ranges from intv cc to v in1 + intv cc . sw1 (pins 19, 20): switch node connection to the inductor of the channel 1 step-down regulator. run 1 ( pin 21): logic controlled run input to channel 1. do not leave this pin floating. logic high activates channel 1 of the step-down regulator. pgood 1 (pin 22): open drain power good indicator for channel 1. ith1 (pin 23): channel 1 error amplifier output and switching regulator compensation pin. connect this pin to appropriate external components to compensate the regulator loop frequency response or connect to intv cc to use the default internal compensation. fb1 (pin 24): feedback input to the error amplifier of the channel 1 step-down regulator. connect resistor divider tap to this pin. the output voltage can be adjusted from 0.6v to 0.99 ? v in1 by: v out1 = 0.6v [1 + (r1/r2)]. ltc 7124 7124fa
8 for more information www.linear.com/LTC7124 block diagram + ? + + ? + ? + ? 1.1ms soft-start comp select slope compensation buck logic and gate drive error amplifier sleep comparator main i-comparator overcurrent comparator reverse comparator intv cc boost1 v in1 sw1 gnd 0.6v fb1 ith1 r th1 c th1 run1 pgood1 mode/sync rt r rt c int r int + ? + + ? + ? + ? 1.1ms soft-start comp select mode select slope compensation buck logic and gate drive error amplifier sleep comparator main i-comparator overcurrent comparator reverse comparator intv cc boost2 sw2 gnd 7124 bd 0.6v fb2 ith2 r th2 c th2 run2 pgood2 gnd c int r int + ? current limit select sync pll and oscillator ldo v in1 v in2 intv cc i lim + ? ltc 7124 7124fa
9 for more information www.linear.com/LTC7124 operation the LTC7124 is a dual-channel, synchronous step-down regulator featuring a constant frequency, peak current mode architecture. it is capable of providing up to 3.5 a of output current across a wide v in range for each channel, while regulating with ultralow quiescent current when no load is present. each channel is enabled by raising its respective run pin voltage above 1v. main control loop in normal operation, the top power switch (n-channel mosfet) is turned on at the onset of a clock cycle. once the inductor current has ramped up to a certain peak value, as determined by the i th voltage, the top power switch turns off, and the bottom switch ( n- channel mosfet) turns on for the remainder of the clock cycle. this i th voltage is the output of the error amplifier, which compares the fb voltage to an internal 0.6 v reference. when the load increases, the fb voltage falls below the reference value, thereby causing the i th voltage to increase until the average inductor current matches the new load current. due to a wide range of possible operating frequencies, the error amplifier can be internally or externally compensated based on the i th pin. the frequency of operation is programmed by the value of the r t resistor. if a clock signal is applied to the mode/ sync pin , an internal phase-locked loop will synchronize the r t programmed frequency to the external clock. if the rt pin is tied to intv cc , spread spectrum operation around 2.25mhz (12%) is enabled, and external clock syncing is not allowed. low current operation at light load current levels, the LTC7124 can automatically transition from continuous operation to one of two dis - continuous conduction modes ( dcms) of operation, if programmed to do so. in both these modes, burst mode and pulse skipping, as long as the i th voltage is lower than the zero current level, the switcher will halt switching and operate in an ultralow quiescent current sleep state. in this sleep state, the part will draw only 5.5 a of quiescent cur - rent from v in1 if only one channel is enabled and 8 a of quiescent current from v in1 if both channels are enabled. when the load increases and pulls the output out of sleep, the part resumes switching in its active state. to optimize efficiency, burst mode can be enabled by tying the mode/ sync pin to intv cc . in burst mode, the minimum peak current level is set to be 800 ma, thereby overriding any i th voltage that commands a lower peak current. to minimize v out ripple, pulse skipping mode can be enabled by grounding the mode/sync pin. in this case, the minimum peak current level is set to be 200 ma, lower than in burst mode. as a result, compared to burst mode, pulse skipping mode produces a lower output voltage ripple, but at a slightly lower efficiency at light loads. if a channel is programmed to operate at half peak current with the i lim pin, the minimum peak current levels likewise scale accordingly by half to 400 ma in burst mode and 100ma in pulse skipping mode. forced continuous mode operation if operating in dcm is undesirable, the LTC7124 can be put in forced continuous mode by tying the mode/sync pin between 1 v and intv cc C1.2v. in forced continuous mode, the part will switch every clock cycle regardless of the value of the output load current. power good status output the pgood pin output indicates whether the output volt - age is within 7.5% of the regulation point. immediately after the output voltage enters this 7.5% window, the pgood output becomes high impedance. conversely, when the output voltage falls out of regulation, the pgood open-drain output is pulled low after a 32 clock cycle delay. high duty cycle/dropout operation as the operating duty cycle of a channel approaches 100%, the part enters dropout operation for that channel. in this very high duty cycle condition, if the bottom power switch has been off for 32 clock cycles, the regulator will automatically turn off the top power switch and turn on the bottom power switch for the last 25% of the next clock cycle to charge the boost-sw capacitor. ltc 7124 7124fa
10 for more information www.linear.com/LTC7124 operation as the boost-sw capacitor depletes charge, the gate drive voltage for the top power switch decreases, which increases the r ds(on) . at heavy loads, this increased r ds(on) can result in excessive power dissipation. while this scenario is avoided through the forced refresh of the boost-sw capacitor, the maximum duty cycle of the regulator is limited to 99%. if the part is programmed for either burst mode or pulse skipping mode, the regulator will transition in and out of the sleep state as needed to keep the output voltage in regulation. minimum on-time considerations the minimum on-time is the smallest amount of time that the LTC7124 can turn on the top power mosfet, trip the peak current comparator and turn off the top power mosfet. as specified in the electrical characteristics table , this time is typically 50 ns. as a result, the minimum duty cycle can be calculated as: dc min = f ? t on(min) where t on(min) is the minimum on time. as seen in the equation above, decreasing the operating frequency loos- ens the minimum duty cycle constraint. for a given v in , the lowest output voltage for which the switcher can maintain regulation is as follows: v out(min) = v in ? f ? t on(min) in the case where the minimum duty cycle constraint is violated, the output voltage will not be in regulation and generate an overvoltage condition. in both dcms, the switcher will remain in sleep mode until the output voltage falls out below the desired regulation voltage. in forced continuous mode, an overvoltage condition will halt switching until the output decreases to within 7.5% of the desired regulation voltage. input overvoltage protection to protect the power mosfets from transient spikes, the input supply voltage of each channel is continually monitored. when the input voltage exceeds 18.4 v, the regulator suspends switching and resets the internal soft-start capacitor . once the input voltage has fallen below 18 v, the regulator will resume normal switching operation, if its respective run pin is tied high. low supply operation to ensure that the regulator will operate properly, the LTC7124 incorporates an undervoltage lockout circuit, which shuts down both channels when v in1 drops below 3.1v . once v in1 rises above this lower limit, both switchers will resume normal operation if their respective run pins are enabled. nevertheless, the r ds(on) of the power switches may be slightly higher due to lower gate drive depending on the value of v in1 ( see r ds(on) vs input supply voltage graph). soft-start the LTC7124 has an internal 1100 s soft start ramp. during this soft-start period, the part will operate in pulse- skipping mode regardless of the mode programmed by the mode/sync pin. once the soft-start period is complete, the part will transition into the desired mode of operation. ltc 7124 7124fa
11 for more information www.linear.com/LTC7124 figure 1. setting the output voltage figure 2. r rt vs frequency v out cff r1 r2 7124 f01 fb gnd LTC7124 output voltage programming for non-fixed output voltage parts, the output voltage is set by an external resistive divider according to the fol - lowing equation: v out = 0.6v 1 + r1 r2 ? ? ? ? ? ? the LTC7124 also has the capability to sync to an external frequency within 25% of the rt -programmed frequency when a clock signal is applied to the mode/sync pin. when sync is engaged, the part operates in forced con - tinuous mode. applications information programing switching frequency connecting a resistor from the rt pin to gnd sets the switching frequency between 500 khz and 4 mhz based on the graph in figure 2. table 1. inductor selection table inductor inductance (h) dcr (m) max current (a) dimensions (mm) height (mm) manufacturer ihlp-2020bz-01 series 0.22 0.33 0.47 0.68 1 4.9 7.6 8.9 11.2 18.9 15 12 11.5 10 7 5.2 5.5 5.2 5.5 5.2 5.5 5.2 5.5 5.2 5.5 2 2 2 2 2 vishay www.vishay.com xal 4020 series 0.6 1 1.5 2.2 9.5 13.25 17.75 21.45 8.7 7.9 7.1 5.6 4 4 4 4 4 4 4 4 2.1 2.1 2.1 2.1 coilcraft www.coilcraft.com xal 4030 series 3.3 35.2 5.5 4 4 3.1 xal5030 series 1 2.2 3.3 4.7 6.8 8.5 13.2 21.2 36 26.75 14 9.2 8.7 6.7 6 5 5 5 5 5 5 5 5 5 5 3.1 3.1 3.1 3.1 3.1 rlf7030 series 1 1.5 7.3 8 6.4 6.1 6.9 7.3 6.9 7.6 3.2 3.2 tdk www.tdk.com dfe201610e series 0.24 0.33 16 21 7 6.1 2 1.6 2 1.6 1 1 murata www.murata.com dfe201512e series 0.24 0.33 0.47 13 15 20 6 5.7 5 2 1.6 2 1.6 2 1.6 1.2 1.2 1.2 ltc 7124 7124fa 1 2 3 4 5 frequency (mhz) 7124 f02 r rt (k) 0 50 100 150 200 250 0
12 for more information www.linear.com/LTC7124 tying the rt pin to intv cc will enable spread spectrum operation around 2.25mhz (12%). doing so will also disable the frequency sync function as well as place the part in the forced continuous mode of operation. in the LTC7124, the two channels operate 180 out of phase. internal/external loop compensation the LTC7124 features both internal and external loop compensation options, allowing the user to optimize the transient response of the regulator based on operating frequency. tying the ith pin of a channel to intv cc will se- lect the internal compensation network, which is designed to be stable at all operating frequencies. for a faster loop transient response, external loop compensation network components can be connected to the ith pin of a chan - nel to enable external loop compensation. external loop compensation is recommended for switching frequencies at 1mhz or higher. inductor selection in addition to the desired input and output voltages, the inductor value and operating frequency determine the inductor ripple current. i l = v out f l 1 ? v out v in ? ? ? ? ? ? based on the equation, a higher inductor value or a higher operating frequency will lower the inductor ripple current. decreasing the inductor ripple current reduces power loss in the inductor, esr losses in the output capacitors, and the output voltage ripple, thereby boosting efficiency. thus, as high efficiency necessitates a large inductor, an inherent tradeoff exists among component size, efficiency , and operating frequency. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . to guarantee that ripple current does not exceed a specified maximum, the induc- tance should be chosen according to: l = v out f i l(max) 1 ? v out v in(max) ? ? ? ? ? ? once the value for l is known, the type of inductor must be selected. actual core loss is independent of core size for a fixed inductor value, but is very dependent on inductance selected. as the inductance or frequency increases, core losses decrease. however, the increased turns of wire required for larger inductances and higher operating frequencies result in higher copper losses. ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can con - centrate on copper loss and preventing saturation. ferrite core material saturates hard, meaning that the induc- tance collapses abruptly when the peak design current is exceeded. when this occurs, the inductor ripple current (and consequently the output voltage ripple) abruptly increases. for this reason, it is key to ensure that the core will not saturate. different core materials and shapes will change the size/ current and price/ current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/emi requirements. table 1 gives a sampling of available sur face mount inductors. checking transient response the loop response can be checked by looking at the transient response to a load step. when external compensation is utilized, the ith pin allows for optimization of the control loop behavior by providing a dc-coupled and ac filtered closed loop response test point. the dc step, rise time, and settling behavior at this test point reflect the close loop response. assuming a predominantly second- order system , phase margin and/or damping factor can be estimated using the percentage of overshoot seen on the ith pin. when the load current is stepped, switching regulators take several cycles to respond. immediately after the step, v out shifts by an amount equal to i load ? esr, where esr is the effect series resistance of c out . i load also begins to charge or discharge c out generating a feedback applications information ltc 7124 7124fa
13 for more information www.linear.com/LTC7124 error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/dc ratio cannot be used to determine phase margin. the addition of a feedforward capacitor can improve the high frequency response, by providing a phase lead due to the creation of a high frequency zero with r1 in figure 1. the stability of the closed-loop system will determine the output voltage settling behavior. ltpowercad ? and ltspice ? can be used to check control loop and transient performance. in some applications, a more severe transient can be caused by switching in loads with large (>1 f) load capacitors. the discharged load capacitors are effectively put in paral - lel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap controller is designed specifically for this purpose and usually incorporates current limiting , short-circuit protection and soft-starting. input capacitor (c in ) selection the input capacitance, c in , filters the square wave current at the drain of the top power mosfet. to prevent large voltage transients from occurring, a low esr input capacitor sized for the maximum rms current is recommended. the maximum rms current is given by: i rms = i out(max) v out v in ? v out ( ) v in this formula has a maximum at v in = 2v out where i rms = i out 2 this simple worst- case condition is commonly used for design because even significant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life, which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. for low input volt - age applications , sufficient bulk input capacitance is needed to minimize transient effects during output load changes. output capacitor (c out ) selection the selection of c out is determined by the effective series resistance ( esr) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response. the output ripple v out is approximated by: v out < i l esr + 1 8 f c out ? ? ? ? ? ? the output ripple is highest at maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirement. dry tantalum, special polymer, aluminum electrolytic, and ceramic capacitors are all available in surface mount packages. special polymer capacitors are very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switch - ing power supplies. aluminum electrolytic capacitors have significantly higher esr but can be used in cost sensitive applications provided that consideration is given to ripple current ratings and long- term reliability. ceramic capacitors have excellent low esr characteristics and small footprints. when using low- esr ceramic capacitors, the output capacitor value should be chosen to fulfill a charge storage requirement. during load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. the time required for the feedback loop to respond is dependent on the compensation and the output capacitor size. typically , 3 to 4 cycles are required to respond to a load step, but only in the first cycle applications information ltc 7124 7124fa
14 for more information www.linear.com/LTC7124 does the output drop linearly. the output droop v droop is usually about 3 times the linear drop of the first cycle. thus, a good place to start is the with the output capacitor size of approximately: c out = 3 i out f v droop depending on load step requirements and the duty cycle, more capacitance may be required. the actual v droop should be verified by applying a load step to the output. using ceramic input and output capacitors higher value, lower cost ceramic capacitors are available in small case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, due to the self- resonant and high -q characteristics of some types of ceramic capacitors, care must be taken when these capacitors are used at the input. when a ceramic capacitor is used at the input and the power is supplied by a wall adaptor through long wires, a load step at the output can induce ringing at the v in input. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. when choosing the input and output ceramic capacitors, choose the x5r and x7r dielectric formulations. these dielectrics have the best temperature and voltage character- istics of all the ceramics for a given value and size. int v cc regulator bypass capacitor an internal low dropout ( ldo) regulator produces a 3.6v supply, which powers the internal active circuitry and the gate drive for the internal power mosfets. the intv cc pin connects to the output of the ldo regulator and requires a ceramic decoupling capacitor of at least 2.2 f connected to ground. boost capacitor in the LTC7124, an internal bootstrap circuit generates a voltage rail above the input voltage v in to create the gate drive for the top power switch. each time the bottom power mosfet is turned on, a boost capacitor c boost , connected between the boost and sw pins, is charged up to intv cc . during the next clock cycle, when the top power mosfet is turned on, the boost pin voltage will then be approximately v in + intv cc . due to the low amounts of current drawn from the boost rail during operation, a boost capacitance of 0.1f will be sufficient for most applications. efficiency considerations the percentage efficiency of a switching regulator is equal to the output power divided by the input power multiplied by 100%. analyzing individual losses can help identify those that limit efficiency as well as changes that produce most improvement. percent efficiency can then be expressed as: % efficiency = 100% C (loss1 + loss2 + ) where loss1, loss2, etc. are individual losses as a percentage of input power. while all lossy elements will contribute to overall power dissipation, the main losses are the result of i 2 r losses, switching and biasing losses, and other hidden losses. 1. i 2 r losses are calculated from the dc resistances of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current flows through inductor l but is chopped between the internal top and bottom power mosfets. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = r ds(on)top ? dc + r ds(on)bot ? (1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus to obtain i 2 r losses: i 2 r losses = i out 2 (r sw + r l ) 2. the switching current is the sum of the mosfet driver and control currents powered off the intv cc rail generated by the internal ldo. the power mosfet driver current results from switching the gate capacitance of the power mosfets. each time a power mosfet gate is switched from low to high to low again, a packet of charge d q moves from v in to ground. the resulting applications information ltc 7124 7124fa
15 for more information www.linear.com/LTC7124 d q/d t is a current out of intv cc that is typically much larger than the dc control bias current. in continuous mode, i gatechg = f (q t + q b ), where q t and q b are the gate charges of the internal top and bottom power mosfets, respectively, and f is the switching frequency. the power loss is thus: switching loss = i gatechg ? v in1 the gate charge loss is proportional to v in1 and f, and thus these losses will be more pronounced at higher supply voltages and higher frequencies. 3. other hidden losses such as transition loss and copper trace and internal load resistances can account for additional efficiency degradations in the overall power system. it is very important to include these system level losses in the design of the system. transition loss arises from the brief amount of time the top power mosfet spends in the saturated region during switch node transitions. the LTC7124 internal power devices switch quickly enough that these losses are not significant compared to other sources. these losses plus other losses, include diode conduction losses during dead- time and inductor core losses, generally account for less than 2% total additional loss. thermal conditions in most applications , the LTC7124 will not dissipate much heat due to its high efficiency. however, power dissipation can increase significantly when the part is running at high v in , high ambient temperature, high switching frequency, and/or maximum output load. if enough heat is dissipated such that the maximum junction temperature of 160 c is exceeded, the part will shut down until the temperature falls by at least 15 c. when the part recovers from an overtemperature condition, the switchers will resume normal operation, if enabled, in the soft-start state. to prevent an overtemperature condition, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the temperature rise is given by: t rise = p d ? ja as an example, consider the case when the LTC7124 is used in applications where v in1,2 = 12 v, i out1,2 = 3 a, f = 1 mhz, and v out1,2 = 1.8 v. the equivalent power mosfet resistance r sw for both channels is: r sw = r ds(on)top v out v in + r ds(on)bot 1? v out v in ? ? ? ? ? ? =80m 1.8v 12v +40m 1? 1.8v 12v ? ? ? ? ? ? = 46 m the v in 1 current during 1 mhz forced continuous operation with no load is about 5 ma, which includes switching and internal biasing current loss, transition loss, inductor core loss and other losses in the application. the total power dissipated by the part can then be calculated to be: p d = i out1 2 ? r sw1 + i out2 2 ? r sw2 + v in1 ? i in(q) = 3a 2 ? 46m + 3a 2 ? 46m+ 12v ? 5ma = 0.888w the qfn 3 mm 5 mm package junction to ambient tem- perature resistance, ja , is around 22 c/w. therefore, the junction temperature of the regulator operating in a 25c ambient temperature environment is approximately: t j = 0.888w ? 22c/w + 25c = 44.5c since the above calculation is dependent on the r ds(on) at 25 c, the junction temperature rise can be recalculated to account for the positive temperature dependence of the r ds(on) . assuming a 5% rise in the r ds(on) at 44.5c results in a slightly higher junction temperature of 45.5 c. if the application calls for a higher ambient temperature and/or higher switching frequency, care should be taken to reduce the temperature rise of the part by using a heat sink or forced air flow. board layout considerations when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC7124. check the following in your layout: 1. do the capacitors c in1 and c in2 connect to the v in1 and v in2 pins respectively and gnd pins as close as possible? these capacitors provide the ac current to the internal power mosfets and their drivers. applications information ltc 7124 7124fa
16 for more information www.linear.com/LTC7124 because efficiency and quiescent current is important at both high and low load currents, burst mode operation will be utilized. the i lim pin is grounded to allow for maximum output current on both channels. to set a frequency of 2.25 mhz, a 40.2 k resistor is con - nected between the rt pin and gnd based on figure 2. based on the frequency, the inductor value for channel 1 for 40% ripple current can be calculated as follows: l 1 = 1.8v 2.25mhz 1.4a ( ) 1? 1.8v 13.2v ? ? ? ? ? ? = 0.49h a standard value of 0.47 h inductor would work well here. using the same method for channel 2 results in an inductor value of 0.75 h, use a standard value of 0.82 h inductor. c out is selected based on the esr that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. allowing for a v droop of 5% ? v out , the output capacitance necessary for channel 1 can be calculated thusly: c out1 = 3 3.5a 2.25mhz 0.05 1.8v ( ) = 52f a standard capacitance of 68 f or 100 f would work well here. assuming the same v droop for channel 2 results in a calculated c out2 of 28 f. a standard capacitance of 33f or 47f would be suitable here. the input capacitances c in1 and c in2 should be sized for a maximum current rating calculated from the i rms equation given previously. for channel 1, i rms1 = 3.5a 1.8v 13.2v 13.2v 1.8v ? 1 = 1.20a likewise, for channel 2, i rms2 is calculated to be 1.5 a. decoupling each v in pin with a 47 f capacitor is adequate for most applications. applications information 2. are c out1,2 and l 1,2 closely connected? the (C) plate of c out1,2 returns current to gnd. 3. the resistive divider, r1 and r2, of each channel must be connected between the (+) plate of c out and a ground line terminated near gnd. the feedback signals, v fb1 and v fb2 , should be routed away from noisy components and traces, such as the sw1 and sw2 lines, and their traces should be minimized. keep r1 and r2 close to the ic. 4. solder the exposed pad (pin 25) on the bottom of the package to the gnd plane. connect this gnd plane to the other layers with thermal vias to help dissipate heat from the LTC7124. 5. keep sensitive components away from the sw1 and sw2 pins. the feedback resistors and intv cc bypass capacitors should be routed away from the sw1 and sw2 traces and the inductors. 6. a ground plane is preferred. 7. flood all unused areas of all layers with copper, which will help reduce the temperature rise of power compo- nents. the copper areas should be connected to gnd. please refer to figure 3 for a sample pcb layout. design example as a design example, consider using the LTC7124 in an application with the following specifications: v in1,2 = 10.8v to 13.2v v out1 = 1.8v v out2 = 3.3v i out1,2(max) = 3.5a i out1,2(min) = 0a f sw = 2.25mhz ltc 7124 7124fa
17 for more information www.linear.com/LTC7124 applications information 5v/3.3v series output 2.25mhz step-down converter figure 3. sample pcb layout ltc 7124 7124fa r 1 10k r 2 619k r 3 84.5k c boost2 0.1f c out2 100f c in1 r 4 619k r 5 137k l 2 0.82h l 1 1.0h c ff1 33pf 47f c ff2 47pf r rt 40.2k r th2 20k c thp2 10pf c th2 470pf c intvcc r th1 10k c th1 470pf c thp1 10pf c in2 10f LTC7124 v in1 2.2f v in2 run1 run2 ilim gnd fb1 fb2 7124 ta02 sw1 sw2 c boost1 boost1 boost2 pgood1 intv cc ith1 ith2 rt mode/sync v out1 5v at 1.5a + i in2 0.1f v out2 3.3v at 1.5a v in1 12v c out1 100f
18 for more information www.linear.com/LTC7124 applications information 3.3v/2.5v step-down regulator with spread spectrum ltc 7124 7124fa r 3 619k r 4 196k l 2 0.68h c ff2 22pf c boost1 0.1f c in c out1 100f r 1 619k r 2 137k l 1 0.82h c ff1 22pf 47f r th2 16k c th2 220pf c thp2 10pf r th1 15k c th1 220pf 2.2f c thp1 10pf LTC7124 v in1 v in2 run1 run2 ilim gnd fb1 c intvcc fb2 7124 ta03 sw1 sw2 boost1 boost2 intv cc ith1 ith2 rt c boost2 mode/sync v out1 3.3v at 3.5a v out2 2.5v at 3.5a v in 12v x2 pgood1 pgood2 0.1f c out2 100f
19 for more information www.linear.com/LTC7124 1.2v 1mhz dual-phase single output step-down regulator applications information ltc 7124 7124fa 100k c boost2 0.1f c out 100f 2 r1 619k r2 c 619k l 2 1.0h l 1 1.0h c ff 56pf in LTC7124 7124 ta04 v in1 v in2 run1 run2 ilim gnd 47f fb1 fb2 sw2 sw1 ith1 ith2 boost2 r ith 9.09k c ith 1nf c thp 10pf 2.2f intv cc rt mode/sync v out 1.2v at 7a v in 10.8v to 13.2v c x2 c boost1 0.1f boost1 intvcc r rt
20 for more information www.linear.com/LTC7124 package description 3.00 0.10 0.50 bsc 1.50 ref 5.00 0.10 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 5) 0.40 0.10 pin 1 id 0.50 0.10 1 8 13 20 21 24 9 12 bottom view?exposed pad 3.50 ref 0.80 0.40 0.75 0.05 r = 0.110 typ 0.25 0.05 0.50 bsc 0.31 0.23 0.200 ref 0.00 ? 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 3.50 ref 4.10 0.05 5.50 0.05 1.50 ref 2.10 0.05 3.50 0.05 package outline 0.50 bsc udd package 24-lead plastic qfn (3mm 5mm) (reference ltc dwg # 05-08-1537 rev ?) exposed pad variation aa (udc24) qfn 0316 rev ? 0.40 0.31 0.23 0.40 0.80 please refer to http://www .linear.com/product/LTC7124#packaging for the most recent package drawings. ltc 7124 7124fa
21 for more information www.linear.com/LTC7124 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 10/17 electrical characteristics comments C changed to note 3 modified i lim peak current limit values modified programming switching frequency section 3 3 11 ltc 7124 7124fa
22 for more information www.linear.com/LTC7124 ? linear technology corporation 2017 lt1017 rev a ? printed in usa www.linear.com/LTC7124 related parts typical application 5v/1.2v 1mhz step-down regulator with external loop compensation part number description comments ltc3621/ ltc3621-2 1a, 17v, 1/2.25mhz, synchronous step-down regulator 95% efficiency, v in : 2.7v to 17v, v out(min) = 0.6v, i q = 3.5a, i sd < 1a, 2mm 3mm dfn-6, msop-8e ltc3622/ ltc3622-2/ ltc3622-23/5 dual 1a, 17v 1mhz/2.25mhz synchronous step- down regulator 95% efficiency, v in : 2.7v to 17v, v out(min) = 0.6v, i q = 5a, i sd 1a, 5mm 4mm dfn-14 and 16-lead msop package ltc3624/ ltc3624-2 2 a, 17v, 1mhz/2.25mhz synchronous step-down regulator 95% efficiency, v in : 2.7v to 17v, v out(min) = 0.6v, i q = 3.5a, i sd < 1a, 3mm 3mm dfn-8 package ltc3636/ ltc3636-1 dual channel 6a, 20v monolithic synchronous step-down regulator 95% efficiency , v in : 3.1 v to 20v , v out( min) = 0.6v ( ltc3636), 1.8v ( ltc3636-1), i q = 1.3ma, i sd < 13a, 4mm 5mm qfn-28 ltc3633/ ltc3633a 15v/20v, dual 3a (i out ), 4mhz synchronous step-down dc/dc converter 95% efficiency, v in : 3.6v to 15v, v out(min) = 0.6v, i q = 500a, i sd < 13a, 4mm 5mm qfn-28, tssop-28e ltc 3616 6a, 4mhz monolithic synchronous step-down dc/dc regulator 95% efficiency, v in : 2.25v to 5.5v, v out(min) = 0.6v, i q = 1.3ma, i sd < 75a, 3mm 5mm qfn-24 ltc 3605/ ltc3605a 15v/20v, 5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 4v to 15v, v out(min) = 0.6v, i q = 2ma, i sd < 15a, 4mm 4mm qfn-24 ltc 3603 15v, 2.5a (i out ), 3mhz, synchronous step-down dc/ dc converter 95% efficiency, v in : 4.5v to 15v, v out(min) = 0.6v, i q = 75a, i sd < 1a, 4mm 4mm qfn-20, msop-16e ltc 3604 15v, 2.5a (i out ), 4mhz, synchronous step-down dc/ dc converter 95% efficiency, v in : 3.6v to 15v, v out(min) = 0.6v, i q = 300a, i sd < 15a, 3mm 3mm qfn-16, msop-16e ltc 3626 20v, 2.5a synchronous monolithic step-down regulator with current and t emperature monitoring 95% efficiency, v in : 3.6v to 20v, v out(min) = 0.6v, i q = 300a, i sd < 15a, 3mm 4mm qfn-20 ltc 7124 7124fa c out2 100f r3 619k r4 619k l 2 1.5h c ff2 33pf c in r th2 15k c th2 680pf c thp2 10pf r th1 7.326k c th1 470pf 47f c thp1 10pf c boost1 0.1f c out1 100f r1 619k r2 84.5k 2.2f l 1 2.2h c ff1 22pf LTC7124 v in1 v in2 run1 run2 ilim c intvcc gnd fb1 fb2 7124 ta05 sw1 sw2 boost1 boost2 intv cc ith1 r rt ith2 rt mode/sync v out1 5v at 3.5a v out2 1.2v at 1.75a v in 12v x2 100k c boost2 0.1f

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